1. Field of the Invention
The present invention relates to a gate array integrated semiconductor device, and more particularly, to the stabilization of power supply potentials.
2. Description of the Related Art
In a gate array integrated semiconductor device, a large number of unit cells are regularly formed within a semiconductor in advance, and thereafter, as customers demand, interconnections are formed within each of the unit cells and between the unit cells. In such a gate array integrated semiconductor device, there are always unused unit cells where transistors are not operated. Generally, 20 to 40 percent of the unit cells are unused.
In a prior art gate array integrated semiconductor device, no interconnections are formed within the unused unit cells, even when bypass connections, which pass through the unused unit cells, are formed. This will be explained later.
On the other hand, as the integration of gate array integrated semiconductor devices has recently been developed by using a fine structure technology, the width of connections including power supply connections has become smaller, and the operation speed has become higher, to increase transient currents. Therefore, the potentials at power supply lines such as a ground potential (GND) connection and a positive power supply (Vcc) connection are fluctuated, and accordingly, these power supply potentials supplied to the unit cells are fluctuated. Particularly, when using a 0.6 .mu.m rule, the positive power supply potential is reduced from 5 V to 3.3 V, so that the above-mentioned fluctuation of the power supply potentials is serious.
Note that the fluctuation of the power supply potentials can be compensated for a little by using a junction capacity between an impurity region (well) and a semiconductor substrate. However, in a silicon on insulator (SOI) configuration or a separation by implanted oxygen (SIMOX) configuration, since such a junction capacity is not present, the fluctuation of the power supply potentials is more serious.